I don’t 100% understand it, but from what I’ve seen the SRAM in ESP32 is divided into 3 banks with fixed sizes and addresses (192KB, 128KB, and 200KB), with each bank having restrictions as to possible use. For us, available IRAM is a hard limit we are hitting. None of this is very configurable in the original ESP32, and revisions to silicon haven’t changed that. The S2 chips are a step down (seemingly trying to entice people away from the low end old ESP8266), and C3 further emphasises this with pin-to-pin ESP8266 compatibility. The S3 seems intended to be a step up, while still keeping the costs down. I’ve been told that S3 silicon changes this fixed arrangement of RAM. I was referred to the announcement statement “compared with ESP32, it supports larger, high-speed octal SPI flash, and PSRAM with configurable data and instruction cache". But still waiting to see the details. Apart from some early units in the hands of lucky testers, this is all we have: https://www.espressif.com/en/news/ESP32_S3 <https://www.espressif.com/en/news/ESP32_S3> Not even a data sheet. Definitely not a drop-in replacement module anyway, so even with hardware this will be a while away. I am just interested in it because it may give us a relatively smooth expansion path forwards for the three limits we are pushing up against (IRAM/RAM, GPIO, and flash size). There is also the rumour mill: https://www.esp32.com/viewtopic.php?t=18023 <https://www.esp32.com/viewtopic.php?t=18023> I guess we will have to wait and see… Regards, Mark P.S. Wikipedia further confuses the issue (https://en.wikipedia.org/wiki/ESP32 <https://en.wikipedia.org/wiki/ESP32>) by talking about the S3 having “a new microcontroller that features a dual-core Xtensa LX7 CPU core with a clock speed of up to 240MHz, 384 KB of RAM and an additional 384 KB of SRAM”. No idea where they are getting that from (maybe ROM not RAM)?).
On 7 Mar 2021, at 8:11 AM, Stephen Casner <casner@acm.org> wrote:
On Sun, 7 Mar 2021, Mark Webb-Johnson wrote:
Supposedly, sram is now dynamically partitioned and memory usage optimized (including better use of psram). We'll have to see when it actually becomes available.
That sounds more like an OS change than a hardware change. If so, then we just need to get over our update hump.
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