Yes, the SN74LV1T34 we are trying is around that (5ns). 3.3v->1.8v seems to have the worst propagation delay.

At 40MHz, the !CS signal must be established within 25ns, so we’ll be delayed about 1/5 of that cycle. I think that should be ok.

The lines we have are:

Notice that the CLK is different for flash vs SPI RAM access.

My concern is the ‘out’ transition from us to some other device (say SPI RAM) - we could still have CS active for the first 1/5 of that cycle. Not sure how much delay there is when switching between different SPI devices, but I suspect it will not be quick (us rather than ns). In any case, the flash spi clock should not even be running when SPI RAM is being accessed (flash and ram are on two different clocks). Advise from China was that it would be ok. I’ll have a look at it on the oscilloscope when I get it.

The issue is that we can’t really see any other way of doing it. I guess we’ll find out in the next couple of days.

Regards, Mark.

On 19 Jan 2018, at 10:47 AM, Stephen Casner <casner@acm.org> wrote:

On Wed, 17 Jan 2018, Mark Webb-Johnson wrote:

The only solution we can see is to continue to use GPIO22 for FL_CS2
external flash, but use a level converter 3.3V -> 1.8V. We only need
uni-directional, but it must operate fast enough not to interfere
with a 40MHz SPI bus. Maybe a resistor voltage divider would be too
slow / interfere too much, so safer to use a simple single channel
uni-directional 3.3V->1.8V logic level shifter chip.

Just out of curiousity I looked in DigiKey to see what SMD
unidirectional level translators were available.  They all seem to
have typical propagation delays in the neighborhood of 5ns.  Since the
cycle time for 40MHz is 25ns, it seems like that delay would be a
problem.

                                                       -- Steve
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