<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">I don’t 100% understand it, but from what I’ve seen the SRAM in ESP32 is divided into 3 banks with fixed sizes and addresses (192KB, 128KB, and 200KB), with each bank having restrictions as to possible use. For us, available IRAM is a hard limit we are hitting. None of this is very configurable in the original ESP32, and revisions to silicon haven’t changed that. The S2 chips are a step down (seemingly trying to entice people away from the low end old ESP8266), and C3 further emphasises this with pin-to-pin ESP8266 compatibility. The S3 seems intended to be a step up, while still keeping the costs down.<div class=""><br class=""></div><div class="">I’ve been told that S3 silicon changes this fixed arrangement of RAM. I was referred to the announcement statement “c<i class="">ompared with ESP32, it supports larger, high-speed octal SPI flash, and PSRAM with configurable data and instruction cache"</i>. But still waiting to see the details. Apart from some early units in the hands of lucky testers, this is all we have:</div><div class=""><br class=""></div><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;" class=""><div class=""><a href="https://www.espressif.com/en/news/ESP32_S3" class="">https://www.espressif.com/en/news/ESP32_S3</a></div></blockquote><div class=""><div><br class=""></div><div>Not even a data sheet. Definitely not a drop-in replacement module anyway, so even with hardware this will be a while away. I am just interested in it because it may give us a relatively smooth expansion path forwards for the three limits we are pushing up against (IRAM/RAM, GPIO, and flash size).</div><div><br class=""></div><div>There is also the rumour mill:</div><div><br class=""></div></div><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;" class=""><div class=""><div><a href="https://www.esp32.com/viewtopic.php?t=18023" class="">https://www.esp32.com/viewtopic.php?t=18023</a></div></div></blockquote><div class=""><div><br class=""></div><div>I guess we will have to wait and see…</div><div><br class=""></div><div>Regards, Mark</div><div><br class=""></div><div>P.S. Wikipedia further confuses the issue (<a href="https://en.wikipedia.org/wiki/ESP32" class="">https://en.wikipedia.org/wiki/ESP32</a>) by talking about the S3 having “<i class="">a new microcontroller that features a dual-core Xtensa LX7 CPU core with a clock speed of up to 240MHz, 384 KB of RAM and an additional 384 KB of SRAM</i>”. No idea where they are getting that from (maybe ROM not RAM)?).</div><div><br class=""></div><div><blockquote type="cite" class=""><div class="">On 7 Mar 2021, at 8:11 AM, Stephen Casner <<a href="mailto:casner@acm.org" class="">casner@acm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">On Sun, 7 Mar 2021, Mark Webb-Johnson wrote:<br class=""><br class=""><blockquote type="cite" class="">Supposedly, sram is now dynamically partitioned and memory usage<br class="">optimized (including better use of psram). We'll have to see when it<br class="">actually becomes available.<br class=""></blockquote><br class="">That sounds more like an OS change than a hardware change. If so,<br class="">then we just need to get over our update hump.<br class=""><br class=""> -- Steve<br class="">_______________________________________________<br class="">OvmsDev mailing list<br class=""><a href="mailto:OvmsDev@lists.openvehicles.com" class="">OvmsDev@lists.openvehicles.com</a><br class="">http://lists.openvehicles.com/mailman/listinfo/ovmsdev<br class=""></div></div></blockquote></div><br class=""></div></body></html>